1. Field of the Invention
The present invention relates to median filtering apparatuses and methods for use in removing a noise component from an input image in digital image processing.
2. Description of the Related Art
Median filtering is performed in image processing of a multi-value input image. In an M×N window surrounding a pixel being processed (pixel area), the pixel values of M×N pixels are sorted in descending order. The median pixel value (M×N/2-th) is output as the pixel being processed.
An example of a known median filter is described in “The Art of Computer Programming vol. 3, pp. 220 to 246: Sorting and Searching”. In this example, the size of a window is 3×3.
FIG. 4 is a block diagram showing median filtering using a 3×3 window.
Referring to FIG. 4, input image signals 100 to 102 each have a bit length of n. The signal 101 is delayed from the signal 100 by one horizontal period while being at the same vertical pixel position. The signal 102 is delayed from the signal 101 by one horizontal period while being at the same vertical pixel position. Flip-flops 103 to 111 are D-type flip-flops forming a 3-stage shift register. The flip-flops 103 to 111 store and transfer the corresponding input image signals 100 to 102 every clock cycle. Extraction of a signal at each of the stages enables a signal string consisting of nine pixel signals in the 3×3 window to be extracted for signal lines 112 to 120.
Modules 121 to 145, which are indicated by circles and bold vertical lines, represent comparator modules. Each comparator module has a function for comparing the pixel signal values of two input signal lines and for outputting the larger value to the upper signal line and the lower value to the lower signal line. FIG. 5 shows an example of the circuit configuration of the comparator module.
Referring to FIG. 5, n-bit pixel signals are input to signal lines 20 and 21. A comparator 22 outputs a signal value indicating the relationship of the two pixel signal values. On the basis of the signal value, a multiplexer 23 outputs the larger value of the two signals to an output 26. The signal that is output from the comparator 22 and that indicates the relationship in values is inverted by an inverter 25. On the basis of the inverted signal value, a multiplexer 24 outputs the lower value of the two signals to an output 27.
With the provision of the comparator modules 121 to 145, the larger value is selected by the upper portion of the drawing, whereas the smaller value is selected by the lower portion of the drawing. As a result, a data string including the values sorted in descending order is stored in flip-flops 146 to 154. Of the sorted values, the fifth value, that is, the value stored in the flip-flop 150, is output as a median value 155 by the median filtering operation.
The median filtering requires many pieces of hardware. Referring to FIG. 4, 25 comparator modules and 18 flip-flops are used.
The specification of the median value 155 (fifth value) to be output eliminates the necessity of using the comparator modules 144 and 145 for defining the third, fourth, sixth, and seventh values and the flip-flops 146 to 149 and 151 to 154 for storing values other than the median value. Still, the number of stages of comparator modules is large and thus the processing cannot be completed in one clock cycle. It thus becomes necessary to provide one stage of nine flip-flops for storing data. A total of 23 comparator modules and 19 flip-flops are necessary.
Similarly, a 4×4 window requires 54 comparator modules and 34 flip-flops. As M and N become larger, so does the amount of hardware.